An FPGA architecture for high speed edge and corner detection
- 8 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 112-116
- https://doi.org/10.1109/camp.2000.875965
Abstract
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.Keywords
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