Spider: a high-speed network interconnect

1 January 1997

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 17 (1) , 34-39
https://doi.org/10.1109/40.566196

Abstract

SGI's Spider chip-Scalable, Pipelined Interconnect for Distributed Endpoint Routing-create a scalable, short-range network delivering hundreds of gigabytes per second in bandwidth to large configurations. Individual Spider chips sustain a 4.8-Gbyte/s switching rate, connecting to each other and to endpoints across cables up to 5 meters in length. By delivering very high bandwidth-thousands of times higher than standard Ethernet-at low latencies, Spider is ideal for CPU interconnect applications, high-end network switches, or high-performance graphics interconnects. The Spider chip design drew on the principles of computer communications architecture. Isolation between the physical, data link, and message layers led to a well-structured design that is transportable and more easily verified than a nonlayered solution. Because the chip implements all layers in hardware, latency is very low. Thus, we could realize the benefits of layering without sacrificing performance.

Keywords

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