Optimization of epitaxial layers for power bipolar-MOS transistor

1 September 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 7 (9) , 510-512
https://doi.org/10.1109/EDL.1986.26455

Abstract

This is a theoretical study of the effect of epitaxial layer design on the performance of the power bipolar-MOS transistor, also known as IGT and COMFET. A procedure for optimizing the layer thicknesses, doping concentrations, and lifetime is proposed and examples are provided for 500-V devices. The use of a thin (< 5 µm) and rather heavily doped (∼ 1018cm-3) buffer layer can have pronounced beneficial effects on device turn-off speed and a small benefit on the forward voltage. Turn-off time can be much shorter than the carrier lifetime due to a low emitter efficiency. For the same forward-voltage performance, using an optimally designed buffer layer gives much faster device switching speed than using lifetime control. By combining the use of optimally designed epitaxial layer and carrier lifetime reduction, it is possible to achieve 100-ns switching speed while maintaining low forward-voltage drop.

Keywords

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