Double-Edge-Triggered Flip-Flops
- 1 June 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-30 (6) , 447-451
- https://doi.org/10.1109/tc.1981.1675811
Abstract
A conventional positive-edge-triggered flip-flop (FF) senses and responds to the control input or inputs at the time the clock input is changing from 0 to 1. It does not respond at all to changes in the opposite direction. Negative-edge-triggered FF's behave in a complementary manner. Thus, these FF's can respond at most once per clock pulse cycle. It is proposed that double-edge-triggered (DET) FF's, responding to both edges of the clock pulse would have advantages with respect to speed and energy dissipation.Keywords
This publication has 1 reference indexed in Scilit:
- Structural Simplification and Decomposition of Asynchronous Sequential CircuitsIEEE Transactions on Computers, 1969