A CCD line addressable random-access memory (LARAM)
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (5) , 268-272
- https://doi.org/10.1109/JSSC.1975.1050610
Abstract
A novel approach to charge-coupled device (CCD) memory organization has been conceived and implemented in a 16 384-bit memory chip. It utilizes an isoplanar n-channel silicon gate MOS process in conjunction with self-aligned implanted barrier, buried channel CCD technology. The chip is organized in four parallel, identical sections of 32 independent lines with each line 128 bits long. The four sections are controlled in parallel. Any of the 32 lines (the same line in each of the four sections) can be randomly accessed; hence the name, line addressable random-access memory (LARAM). Each line can be brought to a halt at any of its 128 possible positions. Design features and test results of the memory are described.Keywords
This publication has 3 references indexed in Scilit:
- Charge-coupled devices for memory applicationsPublished by Association for Computing Machinery (ACM) ,1975
- A 4160-bit C4D serial memoryIEEE Journal of Solid-State Circuits, 1974
- One-phase CCD: a new approach to charge-coupled device clockingIEEE Journal of Solid-State Circuits, 1972