A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

1 October 1993

journal article
Published by World Scientific Pub Co Pte Ltd in International Journal of Modern Physics C

Vol. 4 (5) , 969-976
https://doi.org/10.1142/s0129183193000744

Abstract

APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.

Keywords

ARCHITECTURE
HARDWARE IMPLEMENTATION
LATTICE
INSTRUCTION
OPTIMIZED
MACHINE
PROCESSORS
APE100

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