Analysis and modeling of bang-bang clock and data recovery circuits
Top Cited Papers
- 30 August 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 39 (9) , 1571-1580
- https://doi.org/10.1109/jssc.2004.831600
Abstract
A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.Keywords
This publication has 2 references indexed in Scilit:
- Jitter in ring oscillatorsIEEE Journal of Solid-State Circuits, 1997
- Clock recovery from random binary signalsElectronics Letters, 1975