Systolic array processing of the Viterbi algorithm
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Information Theory
- Vol. 35 (1) , 76-86
- https://doi.org/10.1109/18.42179
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- VLSI Structures for Viterbi Receivers: Part I--General Theory and ApplicationsIEEE Journal on Selected Areas in Communications, 1986
- VLSI Array processorsIEEE ASSP Magazine, 1985
- Why systolic architectures?Computer, 1982
- Error-Correction Coding for Digital CommunicationsPublished by Springer Nature ,1981
- Special-Purpose Devices For Signal And Image Processing: An Opportunity In Very Large Scale Integration (VLSI)Published by SPIE-Intl Soc Optical Eng ,1980
- Punctured convolutional codes of rate(n-1)/nand simplified maximum likelihood decoding (Corresp.)IEEE Transactions on Information Theory, 1979
- Convolutional codes II. Maximum-likelihood decodingInformation and Control, 1974
- The viterbi algorithmProceedings of the IEEE, 1973
- On the Viterbi decoding algorithmIEEE Transactions on Information Theory, 1969
- Error bounds for convolutional codes and an asymptotically optimum decoding algorithmIEEE Transactions on Information Theory, 1967