Experience with active messages on the Meiko CS-2
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 140-149
- https://doi.org/10.1109/ipps.1995.395925
Abstract
Active messages provide a low latency communication architecture which on modern parallel machines achieves more than an order of magnitude performance improvement over more traditional communication libraries. This paper discusses the experience we gained while implementing active messages on the Meiko CS-2, and discusses implementations for similar architectures. During our work we have identified that architectures which only support efficient remote write operations (or DMA transfers as in the case of the CS-2) make it difficult to transfer both data and control as required by active messages. Traditional network interfaces avoid this problem because they have a single point of entry which essentially acts as a queue. To efficiently support active messages on modern network communication co-processors, hardware primitives are required which support this queue behavior The overcame this problem by producing specialized code which runs on the communications co-processor and supports the active messages protocol. Our implementation of active messages results in a one-way latency of 12.3 /spl mu/s and achieves up to 39 MB/s for bulk transfers. Both numbers are close to optimal for the current Meiko hardware and are competitive with performance of active messages on other hardware platforms.Keywords
This publication has 10 references indexed in Scilit:
- Low-latency communication over ATM networks using active messagesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- HPAM: an active message layer for a network of hp workstationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Active Messages: A Mechanism for Integrated Communication and ComputationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Virtual memory mapped network interface for the SHRIMP multicomputerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The Stanford FLASH multiprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Separating data and control transfer in distributed operating systemsPublished by Association for Computing Machinery (ACM) ,1994
- CMMD: Active messages on the CM-5Parallel Computing, 1994
- TAM - A Compiler Controlled Threaded Abstract MachineJournal of Parallel and Distributed Computing, 1993
- LogP: towards a realistic model of parallel computationPublished by Association for Computing Machinery (ACM) ,1993
- TPublished by Association for Computing Machinery (ACM) ,1992