A HIGH PERFORMANCE LIQUID-NITROGEN CMOS SRAM TECHNOLOGY

1 September 1988

journal article
Published by EDP Sciences in Le Journal de Physique Colloques

Vol. 49 (C4) , C4-25
https://doi.org/10.1051/jphyscol:1988403

Abstract

A 3.5 ns ECL-compatible 64Kb liquid-nitrogen CMOS (LN-CMOS) SRAM technology with 2.5V power-supply voltage is described. Key features of this high performance 0.5µm-channel LN-CMOS SRAM technology optimized for 77K operation include 0.6µm optical lithography for the gate level, dual polysilicon work functions, retrograde n-well, low resistance arsenic and boron source/drain diffusions, self-aligned titanium silicide, and two-level metal interconnects. For the first time, the leverage of liquid nitrogen CMOS with 2.3X chip level performance improvement at 77K over room temperature CMOS is demonstrated

Keywords

SRAM TECHNOLOGY
CMOS SRAM
HIGH PERFORMANCE LIQUID
LIQUID NITROGEN CMOS

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