A Note on Three-Valued Logic Simulation

1 April 1972

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-21 (4) , 399-402
https://doi.org/10.1109/tc.1972.5008985

Abstract

In this note we discuss a few attributes and pitfalls of three-valued (0, 1, u) digital logic simulation. The areas covered include hazard and race detection, fault detection, verifying the reset logic of a machine, and the problems encountered with self-timing circuits and in employing a complement for u.

Keywords

INTEGRATED CIRCUIT MODELING
HAZARDS
BIOLOGICAL SYSTEM MODELING
LOGIC GATES
COMPUTATIONAL MODELING
FLIP-FLOPS
LATCHES

This publication has 3 references indexed in Scilit:

Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers, 1970
A three-value computer design verification system
IBM Systems Journal, 1969
Hazard Detection in Combinational and Sequential Switching Circuits
IBM Journal of Research and Development, 1965