Large-signal subthreshold CMOStransconductance amplifier

27 April 1995

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 31 (9) , 718-720
https://doi.org/10.1049/el:19950504

Abstract

A folding architecture for a subthreshold CMOS transconductance amplifier is described in the Letter. Good linearity is obtained for an extremely large differential input voltage, without loss in the common-mode voltage range. Theoretical noise analysis indicates a 6 dB improvement in the dynamic range compared to a simple single-pair MOS implementation. A prototype has been fabricated in a 2 µm CMOS process, and experimental results are presented.

Keywords

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