WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
- 1 April 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15453421,p. 80-89
- https://doi.org/10.1109/rtas.2008.6
Abstract
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately obtain the worst-case execution time (WCET) of applications running on multi-core platforms, which is very challenging due to the possible runtime inter-core interferences in using shared resources such as the shared L2 caches. As the first step toward time-predictable multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst- case shared L2 instruction cache misses by considering inter-thread instruction conflicts. Also, the WCET of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.Keywords
This publication has 13 references indexed in Scilit:
- Chronos: A timing analyzer for embedded softwareScience of Computer Programming, 2007
- Worst case timing analysis of input dependent data cache behaviorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Cooperative Caching for Chip MultiprocessorsACM SIGARCH Computer Architecture News, 2006
- Real-Time Scheduling on Multicore PlatformsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006
- Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference PatternsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Timing anomalies in dynamically scheduled microprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Cache modeling for real-time software: beyond direct mapped instruction cachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing analysis for data caches and set-associative cachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Integrating the timing analysis of pipelining and instruction cachingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient longest executable path search for programs with complex flows and pipeline effectsPublished by Association for Computing Machinery (ACM) ,2001