A path connection algorithm for multi-layer boards

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Abstract
The design of component interconnection paths on printed plugboards, platters, and backplanes is becoming increasingly critical as the component density and circuit speed increases. At the present time, most of the successful attempts to route multi-layer surfaces have been based on orthogonal wiring patterns where one surface of a pair contains mostly vertical paths and the other surface contains mostly horizontal paths. The two surfaces may be joined, or “stitched”, at specified points by plated (via) holes. This method has produced results ranging from excellent to poor depending on the surface definition, path width, pad size, etc. A fault inherent to orthogonal wiring is a tendency to use an excessive number of via holes. The algorithm proposed in this paper and presently being incorporated in a Design Automation program for RCA Information Systems Division extends a well known “maze running” technique commonly used on single surfaces to multi-layer boards.

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