An electrical mechanism for holding time degradation in dynamic MOS RAM's

1 November 1979

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 26 (11) , 1684-1690
https://doi.org/10.1109/T-ED.1979.19672

Abstract

Holding time degradation due to electrically generated excess minority carriers has been observed in a 16-kbit dynamic MOS RAM. The failure mode is described by two-step impact ionization in a drain depletion region of a transistor and a subsequent diffusion process. Other experiments by a dynamic MOS RAM cell test device, a charge-coupled device, and a He-Ne laser for carder excitation, consistently verify the mechanism which leads to degradation of stored information. In addition, the actual failure map is successfully reproduced by an optical experiment, and also in a computer simulation. Effects of electrical excess minority-carrier generation are discussed from a reliability point of view, particularly for dynamic MOS LSI's.

Keywords

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