A queueing analysis of a symmetric multiprocessor with shared memories and buses
- 1 January 1983
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Proceedings E Computers and Digital Techniques
- Vol. 130 (3) , 83-89
- https://doi.org/10.1049/ip-e.1983.0017
Abstract
The performance of a symmetric multiprocessor system on the level of memory requests is studied. The multiprocessor consists of a number of identical processors, each having its local private memory and each being connected via a system of identical buses to all global memory modules. The system is modelled by a Markovian queueing network and solved approximately by a hierarchical decomposition technique. A closed-form solution for the steady-state probabilities is presented and its numerical properties are discussed. Formulas for computing various performance measures are included. Simple lower and upper bounds for the throughput are derived which converge to the exact value as the number of processors increases.Keywords
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