An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program Flow

1 January 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 31 (6) , 1139-1144
https://doi.org/10.1109/tns.1984.4333471

Abstract

Simulation experiments for determining the effects of single event upsets on microprocessor program flow are described. A 16 bit microprocessor is modeled using a hardware description language. Using pseudorandom selection of event time and effected flip-flop, SEU's are injected into the microprocessor model. Upset detectors are modeled along with the microprocessor for determination of fault coverage of several candidate fault detection techniques.

Keywords

This publication has 3 references indexed in Scilit:

Hierarchical simulation and control of power plants: a case-study approach
Published by Institution of Engineering and Technology (IET) ,1996
The Containment Set Approach to Upsets in Digital Systems
IEEE Transactions on Computers, 1982
GSP: A Logic Simulator for LSI
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981