Performance analysis and design of Banyan network based broadband packet switches for integrated traffic
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1154-1158 vol.2
- https://doi.org/10.1109/glocom.1989.64137
Abstract
Approximate Markov chain models are developed for Banyan-network-based packet switches built with arbitrary node sizes and a single buffer at each of the inputs/outputs of the nodes, in a multiclass traffic environment with priority. Invariance of the total throughput and the average time delay is observed. Dilated Banyan networks are also modeled. Techniques for obtaining the time delay distributions for packets of each traffic class are illustrated. It was observed that the total throughput and the average time delay of all the packets depend only on the total load and not on the traffic mix. The first stage is found to affect the division of throughputs, while the remaining stages merely affect the time delays of the different traffic classes. Dilations provide improvements under certain assumptions.<>Keywords
This publication has 6 references indexed in Scilit:
- Banyan networks for partitioning multiprocessor systemsPublished by Association for Computing Machinery (ACM) ,1998
- Performance of buffered banyan networks under nonuniform traffic patternsIEEE Transactions on Communications, 1990
- Design of a broadcast packet switching networkIEEE Transactions on Communications, 1988
- The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet SwitchingIEEE Journal on Selected Areas in Communications, 1987
- The Performance of Multistage Interconnection Networks for MultiprocessorsIEEE Transactions on Computers, 1983
- Analysis and Simulation of Buffered Delta NetworksIEEE Transactions on Computers, 1981