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Switch-Level Timing Simulation of MOS VLSI Circuits
Home
Publications
Switch-Level Timing Simulation of MOS VLSI Circuits
Switch-Level Timing Simulation of MOS VLSI Circuits
VR
Vasant B. Rao
Vasant B. Rao
DO
David V. Overhauser
David V. Overhauser
TT
Timothy N. Trick
Timothy N. Trick
IH
Ibrahim N. Hajj
Ibrahim N. Hajj
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1 January 1988
book
Published by
Springer Nature
https://doi.org/10.1007/978-1-4613-1709-8
Abstract
No abstract available
Keywords
CMOS
VLSI
ANALOG
COMPLEXITY
ELECTRONIC CIRCUIT
INTEGRATED CIRCUIT
LOGIC
NETWORK
SIMULATION
TRANSISTOR
Cited
Cited by 6 articles
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