A Power-Efficient High-Throughput 32-Thread SPARC Processor

1 January 2006

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 295-304
https://doi.org/10.1109/isscc.2006.1696060

Abstract

The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity. The design combines eight 4-threaded 64b cores, a high-bandwidth crossbar, a shared 3MB L2 Cache and four DDR2 DRAM interfaces. The 90nm 378mm ² die consumes 63W at 1.2GHz. Memory design techniques to support the high bandwidth are also discussed

Keywords

YARN
DELAY
PIPELINES
CLOCKS
REGISTERS
THROUGHPUT
SEMICONDUCTOR DEVICE MEASUREMENT
FREQUENCY
TEMPERATURE MEASUREMENT
SUN

This publication has 1 reference indexed in Scilit:

Niagara: A 32-Way Multithreaded Sparc Processor
IEEE Micro, 2005