Block and track method for automated layout generation of MOS-LSI arrays

1 January 1972

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XV, 62-63
https://doi.org/10.1109/isscc.1972.1155010

Abstract

An automated layout program with a block and track concept will be described. The program, which takes logic descriptions, can generate composite-patterns for single-chip calculator MOS-LSI arrays within 600 seconds computing time with manual-comparable chip areas.

Keywords

LARGE SCALE INTEGRATION
WIRING
LOGIC ARRAYS
EQUATIONS
CALCULATORS
INTEGRATED CIRCUIT INTERCONNECTIONS
LOGIC CIRCUITS
LOGIC DESIGN
AUTOMATIC LOGIC UNITS
HUMANS

This publication has 2 references indexed in Scilit:

Computer-generated IGFET layout using a vertically-packed weinberger arrangement
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1971
An Algorithm for Path Connections and Its Applications
IEEE Transactions on Electronic Computers, 1961