Issues in logic synthesis for delay and bridging faults
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 3101-3104 vol.4
- https://doi.org/10.1109/iscas.1990.112668
Abstract
The synthesis and testing issues for certain nonclassical faults (delay and bridging faults) are considered. Cost versus performance tradeoffs in synthesizing circuits which are robust delay fault testable are first examined. A new type of scan latch design is presented for robust delay fault testability of sequential circuits. The testability of bridging faults in combinational logic is also addressed. Tests are generated using implicit don't cares obtained for the circuit during the synthesis process. A PODEM-based algorithm has been developed for fast detection of a class of bridging faults.<>Keywords
This publication has 5 references indexed in Scilit:
- Synthesis of delay fault testable combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A novel approach to accurate timing verification using RTL descriptionsPublished by Association for Computing Machinery (ACM) ,1989
- Multi-level logic minimization using implicit don't caresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Bridging and Stuck-At FaultsIEEE Transactions on Computers, 1974