ATM input-buffered switches with the guaranteed-rate property
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 331-335
- https://doi.org/10.1109/iscc.1998.702542
Abstract
There is considerable interest in the provision of guaranteed-rate services for IP and ATM networks. Simultaneously, bandwidth demands make input-buffered architectures attractive, and in some cases, necessary. We consider the problem of how to support guaranteed-rate services in a single-stage, input-buffered switch suitable for a LAN switch, an ATM switch or an IP router. Such a switch must be feasible at high transmission speeds, offering both guaranteed-rate performance for CBR channels (e.g. for real-time connections) and best-effort services for traditional data traffic. We consider a switch scheduling mechanism that employs idling hierarchical round-robin (HRR) scheduling and fabric arbitration at the connection-level for guaranteed-rate service using the Slepian-Duguid algorithm. The switch uses cell level arbitration for best-effort service. This overall switch scheduling mechanism is a variation of DEC's AN2 design.Keywords
This publication has 15 references indexed in Scilit:
- Achieving 100% throughput in an input-queued switchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Rate controlled servers for very high-speed networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design of a gigabit ATM switchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design and implementation of a QoS capable switch-routerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Tiny Tera: a packet switch coreIEEE Micro, 1997
- Fair Prioritized Scheduling in an Input-Buffered SwitchPublished by Springer Nature ,1996
- Survey of ATM switch architecturesComputer Networks and ISDN Systems, 1995
- High-speed switch scheduling for local-area networksACM Transactions on Computer Systems, 1993
- The performance analysis of an input access scheme in a high-speed packet switchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Switching and Traffic Theory for Integrated Broadband NetworksPublished by Springer Nature ,1990