Ultrathin gate dielectrics on 150 mm Si wafers via rapid thermal processing

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Abstract
The scalability from 75 to 150 mm silicon wafers of a new oxidation process is discussed. This process is based on rapid thermal processing (RTP) in a controlled oxygen ambient with heating provided by tungsten-halogen lamps, temperature monitored via an optical pyrometer and controlled by a computer. Silicon dioxide films with thicknesses in the range from 45 to 400 Å were obtained at 1150 °C, with a uniformity of 1.5% across the wafers and from wafer to wafer, independent of the wafer size. Electrical characteristics show typical breakdown fields of 15 MV/cm for 100 Å films with a statistical distribution similar to that of furnace oxides. Capacitance–voltage studies show midgap density of states of less than 1×1010 cm−2 eV−1 and ideal flat band voltages.

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