Optimization of Submicron CMOS Differential Pass-Transistor Logic

1 September 1989

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 218-221
https://doi.org/10.1109/esscirc.1989.5468086

Abstract

Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ¿ N ¿ 64) implemented in a 0.8¿m CMOS technology.

Keywords

CMOS LOGIC CIRCUITS
CIRCUIT NOISE
LOGIC CIRCUITS
CMOS TECHNOLOGY
DELAY
VOLTAGE
NOISE REDUCTION
CLOCKS
DYNAMIC RANGE
DEGRADATION

This publication has 2 references indexed in Scilit:

CMOS differential pass-transistor logic design
IEEE Journal of Solid-State Circuits, 1987
FFT scaling in Domino CMOS gates
IEEE Journal of Solid-State Circuits, 1985