A new high density and very low cost reprogrammable FPGA architecture

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Abstract
1. ABSTRACT A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost. It covers a range of 35K to a million usable gates. In addi- tion, it delivers high performance and it is synthesis effi- cient. This architecture is loosely based on an earlier reprogrammable Actel architecture named ES. By changing the structure of the interconnect and by mak- ing other improvements, we achieved an average cost reduction by a factor of three per usable gate. The first member of the family based on this architecture is fabri- cated on a 2.5V standard 0.25μ CMOS technology with a gate count of up to 130K which also includes 36K bits of two port RAM. The gate count of this part is verified in a fully automatic design flow starting from a high level description followed by synthesis, technology mapping, place and route, and timing extraction. 2. OVERVIEW Actel introduced its first reprogrammable FPGA two years ago, the ES family. The ES family addressed the low to medium gate count ranges with good performance but only average cost per gate compared with the other commercial reprogrammable FPGAs. In this paper, we describe Actel's second generation repro- grammable FPGA architecture. This architecture is similar to the earlier ES architecture in terms of its choice of logic blocks, but it has a different interconnect structure. The main motivation for the new architecture has been the desire to improve the ease of use with higher gate counts and lower cost per gate. Ease of use is loosely defined as the ease of place and route success, ability to fix pins, and predictable performance. In this regard, we surpassed our goals by mak- ing it possible to build FPGAs with gate counts of up to a million gates(1) at 0.25μ technology, and up to two million gates at 0.18μ. Furthermore, we achieved a sizeable reduc- tion in the average cost per usable gate by a factor of 3 even excluding the geometry shrink factor. Despite this cost reduction, the new architecture seems to be more robust for ease of use than the ES family. When compared with other state of the art commercial reprogrammable FPGAs, this architecture delivers competitive performance, while deliv- ering the lowest cost per gate. The next section describes the architecture. Section 4 dis- cusses the CAD software that supports this architecture, where we present preliminary results from synthesis, tech- nology mapping, and place and route.

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