Parallel Viterbi decoding by breaking the compare-select feedback bottleneck

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 719-723
https://doi.org/10.1109/icc.1988.13656

Abstract

A solution is presented for implementing the add-compare-select (ACS) unit of a Viterbi decoder by parallel hardware for high data rates. For a fixed processing speed of the given hardware it allows a linear increase in throughput rate by a linear increase in hardware complexity. Thus arbitrary throughput rates can be achieved by linearly adding more parallel hardware elements. A systolic-array implementation of this parallel ACS unit of a Viterbi decoder is presented.<>

Keywords

This publication has 5 references indexed in Scilit:

Design of VLSI Circuits
Published by Springer Nature ,1987
TDM-FDM Transmultiplexer: Digital Polyphase and FFT
IEEE Transactions on Communications, 1974
The viterbi algorithm
Proceedings of the IEEE, 1973
Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
IEEE Transactions on Information Theory, 1967
Applied Dynamic Programming
Published by Walter de Gruyter GmbH ,1962