A 2.4 μm CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz
- 1 January 1989
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 25.4/1-25.4/4
- https://doi.org/10.1109/cicc.1989.56831
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- A novel N-th order IIR switched-capacitor decimator building block with optimum implementationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Concepts for the restitution of video signals using MOS analog circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Optimum implementation of a multistage IIR SC bandpass decimator for a voiceband analogue interface systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- IIR switched-capacitor decimator building blocks with optimum implementationIEEE Transactions on Circuits and Systems, 1990
- Present and future applications of switched-capacitor circuitsIEEE Circuits and Devices Magazine, 1987
- A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communicationIEEE Journal of Solid-State Circuits, 1987
- Nonrecursive polyphase switched-capacitor decimators and interpolatorsIEEE Transactions on Circuits and Systems, 1985
- Novel single-ended CMOS transconductance amplifiersElectronics Letters, 1985