FPGA Implementations of LDPC over GF(2m) Decoders
- 1 October 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21623562,p. 273-278
- https://doi.org/10.1109/sips.2007.4387557
Abstract
Low Density Parity Check (LDPC) codes over GF(2 m ) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2 m ) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2 m ) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2 m ). The results prove that the implementation of LDPC over GF(2 m ) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2 m ) LDPC codes.Keywords
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