Gate oxide breakdown behaviour in a mesa SOI CMOS process
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Form only given. A CMOS process using mesa isolation on lamp-zone-melting recrystallized (ZMR) SOI substrates is discussed. The results of investigations on the gate oxide breakdown behaviour and a technique to improve it when island isolation is used are presented. The technique was used in a 2-μm CMOS process. The gate oxide thickness is 250 A. 16×16 multipliers utilizing 8500 transistors was fabricated on a 4 mm 2 surface. Compared to bulk circuits, they show a 30% improvement in the factor of merit, which is related to the multiplication time and the channel length of the minimal transistors of the circuits Author(s) Haond, M. CNET, Meylan, France Le Neel, O. ; Mascarin, G. ; Gonchond, J.P.Keywords
This publication has 2 references indexed in Scilit:
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- The Oxidation of Shaped Silicon SurfacesJournal of the Electrochemical Society, 1982