200-gate ECL master-slice LSI

1 January 1974

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 62-63
https://doi.org/10.1109/isscc.1974.1155336

Abstract

A 200-gate ECL master slice LSI suitable for computer mainframe logic will be described. Optimization has resulted in a 1.5-ns loaded delay.2.5-W power dissipation and compatibility with standard ECL components.

Keywords

LARGE SCALE INTEGRATION
WIRING
DELAY
POWER DISSIPATION
LOGIC CIRCUITS
VOLTAGE
PACKAGING
PINS
THERMAL RESISTANCE
WIRE

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