Fabrication of NMOS capacitors with a low-voltage coefficient at a silicon foundry

1 January 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 6 (1) , 54-56
https://doi.org/10.1109/EDL.1985.26039

Abstract

The custom integrated circuit design technique pioneered by Mead and Conway [1] is often used for moderately complex digital systems. The fabrication is carried out at a "foundry" where a "standard" NMOS process is applied to the design. In this note, the Mead-Conway technique has been applied to analog circuits with the goal of producing a reasonable quality switched capacitor filter with as few process modifications as possible. Seven chip runs have been carried out at two separate foundries with good and consistent results.

Keywords

FABRICATION
MOS DEVICES
SILICON
FOUNDRIES
APPLICATION SPECIFIC INTEGRATED CIRCUITS
DIGITAL SYSTEMS
ANALOG CIRCUITS
SWITCHING CIRCUITS
SWITCHED CAPACITOR CIRCUITS
FILTERS

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