A performance counter architecture for computing accurate CPI components

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Abstract
A common way of representing processor performance is to use Cycles per Instruction (CPI) 'stacks' which break performance into a baseline CPI plus a number of individual miss event CPI compo- nents. CPI stacks can be very helpful in gaining insight into the be- havior of an application on a given microprocessor; consequently, they are widely used by software application developers and com- puter architects. However, computing CPI stacks on superscalar out-of-order processors is challenging because of various overlaps among execution and miss events (cache misses, TLB misses, and branch mispredictions). This paper shows that meaningful and accurate CPI stacks can be computed for superscalar out-of-order processors. Using interval analysis, a novel method for analyzing out-of-order processor per- formance, we gain understanding into the performance impact of the various miss events. Based on this understanding, we propose a novel way of architecting hardware performance counters for build- ing accurate CPI stacks. The additional hardware for implementing these counters is limited and comparable to existing hardware per- formance counter architectures while being signicantly more ac- curate than previous approaches.

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