A 30M samples/s programmable filter processor

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Abstract
A programmable filter processor (PFP) that overcomes classic digital signal processing problems, such as processing speed, number of taps, flexibility, and volatility, using an EPROM lookup table, circuit solutions, and a 1.2- mu m CMOS technology to achieve a working frequency of 30 MHz with acceptable power dissipation is described. The PFP realizes a large range of finite-impulse-response (FIR) filters using a transposed structure where multipliers are replaced by an EPROM storing the products of all possible inputs by all filter coefficients. Then the EPROM acts like 16 multipliers working in parallel. The 68-kb PFP memory is organized in 256 rows and 272 columns. Each row is partitioned into 16 words, each word corresponding to a single stored product. To optimize the EPROM and to increase the precision of the most significant coefficients, the words have a variable length up to 20 b (corresponding to a 12-b central coefficient). Products are stored in two's complement representation using fixed-point arithmetic. The input data x(n) are assumed to be quantized in 256 levels. corresponding to an 80-b representation. as in most of the video applications.<>

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