A 120 MHz BiCMOS superscalar RISC processor

1 January 1993

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/vlsic.1993.920514

Abstract

Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.

Keywords

BICMOS INTEGRATED CIRCUITS
MICROPROCESSORS
INTEGRATED CIRCUIT DESIGN
PIPELINE ARITHMETIC

This publication has 1 reference indexed in Scilit:

A 200-MHz 64-b dual-issue CMOS microprocessor
IEEE Journal of Solid-State Circuits, 1992