Design of a high-speed arithmetic datapath
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 214-215
- https://doi.org/10.1109/iccd.1988.25693
Abstract
This paper presents the implementation of a 64/32 bit floating-point datapath circuit (WTL3×64). This high-speed CMOS circuit integrates a 2 Kbit six-port register file, an independent 64/32-bit alu, a multiplier, and a divide/square-root unit for IEEE binary floating-point format numbers. It is fabricated using a 1.2 micron two-layer-metal CMOS technology. Operating at 60 ns cycle time, the 165000 transistor/147600 square mil chip provides 33 double-precision Mflops of peak performance. The register file, together with special registers, a flexible input/output interface, features for high level language support, and 1.5 Watts of power facilitate ease of integration of the device into various computer systems Author(s) Birman, M. Weitek, Sunnyvale, CA, USA Chu, G. ; Hu, L. ; McLeod, J. ; Bedard, N. ; Ware, F. ; Torban, L. ; Lim, C.M.Keywords
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