A 4MB on-chip L2 cache for a 90nm 1.6GHz 64b SPARC microprocessor

28 September 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 66-513 Vol.1
https://doi.org/10.1109/isscc.2004.1332596

Abstract

A next-generation 1.6GHz 4-issue CPU supports high-end servers and has a 4MB L2 cache. The chip uses 315M transistors in a 90nm 8M CMOS process with an area of 234mm/sup 2/.

Keywords

MICROPROCESSORS
CLOCKS
CENTRAL PROCESSING UNIT
CIRCUITS
DELAY
DECODING
ERROR CORRECTION CODES
THROUGHPUT
REGISTERS
WIRE

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