Switched-capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance

2 August 1984

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 20 (16) , 663-664
https://doi.org/10.1049/el:19840454

Abstract

A new switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed. The insensitivity to capacitor mismatch permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced due to improvements in technology. Tapped analogue delay lines using such delay elements would be ideal for realising programmable and adaptive filters and equalisers in analogue LSI.

Keywords

FEATURE SIZES
EQUALISERS
SWITCHED-CAPACITOR DELAY CIRCUIT
ANALOGUE LSI
CHIP AREA
CAPACITOR MISMATCH
FILTERS
ANALOGUE DELAY LINES
STRAY CAPACITANCE
DEVICE SCALING

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