1/4- mu m LATID (LArge-Tilt-angle Implanted Drain) technology for 3.3-V operation

Publisher Website

7 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1989.74169

Abstract

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Keywords

This publication has 2 references indexed in Scilit:

A theoretical study of gate/Drain offset in LDD MOSFET's
IEEE Electron Device Letters, 1986
The effect of high fields on MOS device and circuit performance
IEEE Transactions on Electron Devices, 1984