A Multiprocessor Implementation of Relaxation-Based Electrical Circuit Simulation
- 1 January 1984
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 350-357
- https://doi.org/10.1109/dac.1984.1585818
Abstract
The electrical circuit simulation of large integrated circuits is very expensive. New relaxation-based algorithms promise to reduce this cost by exploiting the properties of large networks. However, this speed improvement is not sufficient for the cost-effective analysis of very large circuits. While array processors have helped improve the performance of circuit simulators, further improvement can be achieved by the use of special-purpose multiprocessors. In this paper, the implementation of a relaxation-based circuit simulation algorithm, called Iterated Timing Analysis, on a multi-processor is described. Initial results indicate that this approach has a great deal of potential for reducing the cost of circuit simulation.Keywords
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