Fair dynamic arbitration for a multiprocessor communications bus

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Abstract
The Finite Element Machine (FEM) is an experimental parallel computer consisting of an array of 36 asynchronous microcomputers. One method of interprocessor communication on FEM is a bi-directional parallel bus which uses a dynamic arbitration scheme to increase bus bandwidth. Testing of this bus revealed an in transfer rates for individual processors. The imbalance was traced to a defect in arbiter design, and two criteria were identified which must be met to ensure fair dynamic arbitration. These involve (1) priority sequencing, and (2) the efficiency of the arbiter.

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