A 200 MHz CMOS phase-locked loop with dual phase detectors
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 192-193
- https://doi.org/10.1109/isscc.1989.48255
Abstract
The authors describe a 200-MHz PLL (phase-locked loop) in a 2- mu m CMOS technology employing an untrimmed current-controlled ring oscillator (CCO). Two phase detectors are included: a phase-frequency detector (PFD) for fast acquisition during data preamble (100% pulse density), and a mixer phase detector to lock on actual data (in the presence of missing pulses). Simulation results and experimental data using an external current source suggest that using the bandgap reference, the CCO supply sensitivity will be 4%/V and the CCO temperature coefficient will be about 500 p.p.m./ degrees C. Internal input and output waveforms in lock were measured from buffered test pads with a low-capacitance wideband buffered probe.<>Keywords
This publication has 3 references indexed in Scilit:
- A low-power 128-MHz VCO for monolithic PLL ICsIEEE Journal of Solid-State Circuits, 1988
- MOSIS - A gateway to siliconIEEE Circuits and Devices Magazine, 1988
- A 45-mhz Cmos Phase/frequency-locked Loop Timing Recovery CircuitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988