A Wide-Bandwidth Low-Voltage Pll for Powerpc Microprocessors
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- A PLL clock generator with 5 to 110 MHz of lock range for microprocessorsIEEE Journal of Solid-State Circuits, 1992
- A 200-MHz CMOS phase-locked loop with dual phase detectorsIEEE Journal of Solid-State Circuits, 1989
- Charge-Pump Phase-Lock LoopsIEEE Transactions on Communications, 1980