A Layer Damage Model for Calculating Thermal Fatigue Lifetime of Power Devices

1 April 1986

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE) in 8th Reliability Physics Symposium

No. 07350791,p. 79-86
https://doi.org/10.1109/irps.1986.362114

Abstract

Based on the experimental data during device power cycling, the mechanical behavior of solder material, and by introducing a new concept "layer damage factor ß", the authors have proposed a layer damage model for calculating thermal fatique lifetime of power devices. The model can be used in estimating fatique lifetime, evaluating soldering quality, obtaining accelerated lifetime plot, designing chip backside metallizations, etc. Experimental results have been shown to support the theory.

Keywords

FATIGUE
THERMAL RESISTANCE
THERMAL FACTORS
THERMAL STRESSES
RESISTANCE HEATING
LIFE ESTIMATION
LIFETIME ESTIMATION
SEMICONDUCTOR MATERIALS
FAILURE ANALYSIS
TEMPERATURE

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