Optimized ESD protection circuits for high-speed MOS/VLSI

• 1 April 1985
• journal article
• Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
• Vol. 20  (2) , 594-596
• https://doi.org/10.1109/jssc.1985.1052350

Abstract

Keywords

• VLSI
• CMOS TECHNOLOGY
• ELECTROSTATICS
• ELECTROSTATIC DISCHARGE
• FAILURE ANALYSIS
• DEGRADATION
• VERY LARGE SCALE INTEGRATION
• LOW VOLTAGE