A 256 kbit SOI-full-CMOS-SRAM
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 912-913
- https://doi.org/10.1109/iedm.1989.74204
Abstract
The authors describe a 256-kb SOI full-CMOS SRAM which has a wide operation range of supply voltage, 2-6 V. Full-bit-pass devices have been obtained using bonding SOI (silicon-on-insulator) wafers. The key process parameters are listed. The leakage current of the n- or p-type SOI transistor is less than the measurement limit, 0.1 pA/ mu m. The subthreshold swings are 73 mV/decade for n-channel and 82 mV/decade for p-channel transistors. These characteristics are better than or the same as those of the bulk transistor. The SOI device has a 30% shorter address access time than the bulk device at 2-V supply voltage.<>Keywords
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