A pipelined architecture for parallel image relaxation operations
- 1 November 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 34 (11) , 1375-1384
- https://doi.org/10.1109/tcs.1987.1086060
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- A note on discrete relaxationComputer Vision, Graphics, and Image Processing, 1984
- Self-Timed IC Design with PPL’sPublished by Springer Nature ,1983
- Structured logic design of integrated circuits using the storage/logic array (SLA)IEEE Transactions on Electron Devices, 1982
- A Wavefront Notation Tool for VLSI Array DesignPublished by Springer Nature ,1981
- Scene Labeling by Relaxation OperationsIEEE Transactions on Systems, Man, and Cybernetics, 1976