High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrode
- 11 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.Keywords
This publication has 1 reference indexed in Scilit:
- Band offsets of wide-band-gap oxides and implications for future electronic devicesJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2000