A compressed digital output CMOS image sensor with analog 2-D DCT processors and ADC/quantizer

22 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 184-185,
https://doi.org/10.1109/isscc.1997.585326

Abstract

Progress in CMOS-based image sensors is creating opportunities for a low-cost, low-power one-chip video camera with digitizing, signal processing and image compression. Such a smart camera head acquires compressed digital moving pictures directly into portable multimedia computers. Video encoders using a moving picture coding standard such as MPEG and H.26x are not always suitable for integration of image encoding on the image sensor, because of the complexity and the power dissipation. On-sensor image compression such as a CCD image sensor for lossless image compression and a CMOS image sensor with pixel-level interframe coding are reported. A one-chip digital camera with on-sensor video compression is shown in the block diagram. The chip contains a 128/spl times/128-pixel sensor, 8-channel parallel read-out circuits, an analog 2-dimensional discrete cosine transform (2D DCT) processor and a variable quantization-level ADC (ADC/Q).

Keywords

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