A CMOS bit-level pipelined implementation of an FIR x/sin(x) predistortion digital filter

This publication has 5 references indexed in Scilit:

• The design of multiplierless FIR filters for compensating D/A converter frequency response distortion
  IEEE Transactions on Circuits and Systems, 1988
• A true single-phase-clock dynamic CMOS circuit technique
  IEEE Journal of Solid-State Circuits, 1987
• Parallel bit-level pipelined VLSI designs for high-speed signal processing
  Proceedings of the IEEE, 1987
• NORA: a racefree dynamic CMOS technique for pipelined logic structures
  IEEE Journal of Solid-State Circuits, 1983
• Block implementation of digital filters
  IEEE Transactions on Circuit Theory, 1971